A speculative briefing, labeled as one throughout
Every claim in this briefing is an extrapolation from documented 2026 trends, not a confident forecast — a distinction this briefing maintains explicitly rather than letting speculative framing quietly harden into stated fact partway through. The method is straightforward: take trends this cohort’s other tracks already document with real sourcing, and ask what a rack looks like if each one simply continues along its current trajectory to 2030.
Trend one: the merchant-GPU-only rack is already becoming the exception
This cohort’s companion “eight companies” briefing documents custom ASICs — Broadcom and Marvell’s hyperscaler partnerships specifically — growing alongside Nvidia’s merchant GPUs rather than being displaced by them. Market data already shows this diversification in investor positioning: SOXX’s 112.8% H1 2026 gain outpaced SMH’s 82.1%, a divergence attributed partly to greater relative weighting toward custom-ASIC names [1]. Extrapolated to 2030, a “typical” AI datacenter rack plausibly contains a heterogeneous mix of merchant GPUs and workload-specific custom silicon side by side, rather than a uniform GPU-only design — a continuation, not a reversal, of a trend already visible in 2026.
Trend two: interconnect keeps moving from copper to light
This cohort’s power-and-optics track documents optical interconnect already replacing copper for chip-to-chip and rack-to-rack data movement at the leading edge, driven by the same scaling pressure that will only intensify as cluster sizes grow. Lightmatter’s dual interconnect-and-compute strategy [3] suggests this trend plausibly extends by 2030 from today’s leading-edge early adoption toward a default assumption for any datacenter operating at meaningful AI-training scale — not because copper stops working entirely, but because the power and bandwidth economics increasingly favor light at the scales 2030-era clusters are likely to operate at.
Trend three: the packaging-not-wafers bottleneck reshapes the physical rack
This cohort’s TSMC CoWoS briefing documents advanced packaging capacity, not raw wafer starts, as the binding constraint on accelerator output in 2026. Extrapolated forward, a 2030 rack plausibly reflects several more years of packaging innovation — larger reticle-spanning multi-die packages, denser chiplet integration — pushing more of what used to be separate chips on a board into single, tightly integrated packages. The physical rack of 2030, on this extrapolation, looks less like a collection of discrete chips wired together and more like a smaller number of extremely dense, tightly packaged compute modules.
Trend four: power delivery, not compute, increasingly defines the rack’s limits
This cohort’s power-and-cooling track documents grid interconnection and power delivery, not chip supply, as an emerging binding constraint on datacenter buildout even in 2026. A 2030 extrapolation plausibly sees rack design increasingly organized around power-delivery efficiency — the same backside power delivery innovation covered in this cohort’s Moore’s Law-limits briefing, applied at rack and facility scale — rather than around raw compute density alone, reflecting a broader shift already visible in how hyperscalers describe their $725 billion in 2026 capital spending [2]. TSMC’s own A16 node, targeting H2 2026 specifically around backside power delivery, is the clearest single data point that chip-level and rack-level power architecture are already converging on the same underlying engineering solution [4] — a convergence this extrapolation expects to deepen considerably by 2030 rather than reverse.
What this extrapolation explicitly does not claim
This briefing does not claim any specific company wins this transition, does not claim GPUs disappear entirely by 2030, and does not claim these four trends are the only ones that will matter. It claims something narrower: each of the four trends above is already underway and documented elsewhere in this cohort with real 2026 sourcing, and a datacenter rack in 2030 that simply continues each trend along its current trajectory looks meaningfully different from today’s — heterogeneous rather than GPU-uniform, optically interconnected rather than copper-bound, densely packaged rather than discretely chipped, and power-delivery-constrained rather than purely compute-constrained. That is a grounded extrapolation, not a confident prediction, and the difference between the two is the entire point of labeling it as such throughout.
