The scale, stated precisely

OpenAI’s agreement with Broadcom covers the joint development and deployment of 10 gigawatts of custom AI accelerators alongside Ethernet networking solutions, signed in October 2025, with first deployment targeted for the second half of 2026 using a mix of 3-nanometer and 2-nanometer chip designs [1]. This briefing treats that figure with the quantitative seriousness it deserves rather than repeating it as a single impressive-sounding number.

Sizing 10 gigawatts against the rest of the industry

Ten gigawatts is a genuinely enormous power commitment by the standard of anything else in this cohort. This cohort’s power-infrastructure briefing establishes that total US AI datacenter power capacity reached roughly 29.6 gigawatts by Q4 2025 — meaning a single agreement between two companies covers a figure equivalent to roughly a third of the entire national AI datacenter power base that took the whole industry years to build [4]. Set against AMD’s separately covered 6-gigawatt OpenAI agreement, OpenAI’s combined disclosed accelerator-power commitments across just these two deals alone total 16 gigawatts — evidence that OpenAI is deliberately diversifying its custom-silicon supplier base rather than depending on a single partner for a commitment at this scale.

OpenAI's disclosed custom-accelerator power commitments by partner (GW)
Broadcom 10GW AMD 6GW
Source: Data Center Dynamics / cross-referenced cohort reporting, 2026

The node mix, and what it implies about the timeline

The deal’s use of both 3nm and 2nm designs simultaneously, rather than committing entirely to the newer node, is a pragmatic hedge against exactly the kind of leading-edge capacity constraints this cohort’s foundry-track briefings document — TSMC’s N2 ramp, however unprecedented in pace, is still a finite, allocated resource shared across every major accelerator program in the industry [3]. Designing part of the 10-gigawatt buildout on the more mature, higher-yielding 3nm node reduces schedule risk relative to a pure 2nm bet, at some cost to per-chip efficiency — a trade-off consistent with a company trying to hit a firm H2 2026 deployment date rather than optimize purely for peak performance per chip.

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A Broadcom-designed Ethernet switch bay in a bright datacenter, one switch caught part-withdrawn on its rails, teal fibre cabling feeding into a dense faceplate
Figure 1. The deal covers Ethernet networking as well as the accelerators themselves — a 10-gigawatt cluster is only as fast as the fabric tying it together.Image prompt and art direction by Brecht Corbeel; image generated to that direction.

What actually has to be true for this to ship on time

Four separate physical constraints, each covered in more depth elsewhere in this cohort, all have to resolve favorably simultaneously for a 10-gigawatt deployment to land on the stated H2 2026 timeline: sufficient leading-edge wafer and packaging capacity at TSMC; sufficient HBM supply, already documented as sold out industry-wide for all of 2026; sufficient grid interconnection capacity, with national interconnection queues exceeding 2,100 gigawatts of pending requests and 30-50% of planned 2026 capacity projected to slip to 2028 [5]; and sufficient fiber and optical-networking supply, given that AI racks require 10 to 36 times more fiber than conventional server racks [8]. A shortfall in any single one of these four independently sourced constraints could delay the deployment regardless of how well Broadcom’s own chip design and manufacturing execution performs.

Constraint layer 2026 status
Leading-edge wafer/packaging (TSMC) Capacity growing ~70-80% CAGR but allocation-constrained
HBM memory supply Sold out industry-wide for all of 2026
Grid interconnection 2,100+ GW national queue; 30-50% of 2026 capacity may slip to 2028
Fiber/optical networking 10-36x more fiber per rack; 20+ week lead times

The business context behind the deal

The agreement lands directly inside Broadcom’s broader custom-silicon growth story, covered in this cohort’s companion Broadcom briefing: a reported $73 billion AI backlog and a stated $100 billion annual AI revenue target by 2027 [7]. A single 10-gigawatt commitment from OpenAI represents a very large share of the demand Broadcom needs to hit that target, which is itself worth noting as a concentration risk running in the opposite direction from the ones this cohort typically tracks: not a supplier being a single point of failure for a customer, but a single customer commitment now representing an outsized share of a major supplier’s own forward revenue target. Framed against total 2026 hyperscaler-adjacent AI capital expenditure of roughly $725 billion across the four largest cloud providers alone [6], OpenAI’s Broadcom and AMD commitments combined represent a meaningful, independently verifiable slice of the entire industry’s physical buildout — described, tellingly, by RCR Wireless as signaling “a new era of custom silicon in AI” in its own right [2].

What would falsify the optimistic reading of this deal

If, over the next several quarterly disclosure cycles, Broadcom’s reported backlog conversion into actual shipped, revenue-generating silicon lags materially behind the stated H2 2026 deployment target, that would be the clearest available signal that one or more of the four physical constraints identified above is binding harder than either company’s public messaging currently suggests — a checkable, dated test rather than a permanently open question.