A company that makes everyone else’s product

Nvidia does not manufacture the Blackwell die. Apple does not manufacture the chip inside an iPhone. AMD, Qualcomm, and Broadcom design silicon and hand the design to somebody else to build. That somebody, for the overwhelming majority of the industry’s leading-edge logic, is Taiwan Semiconductor Manufacturing Company — TSMC — and the fact that this arrangement feels unremarkable today is itself the story. In 1987, when Morris Chang founded TSMC as a company that would manufacture chips designed entirely by other firms and design none of its own, it was a genuinely strange idea [4]. Integrated device manufacturers like Intel and NEC only sold spare fabrication capacity to outsiders opportunistically, when their own production lines had room. A company built from the ground up to be everyone else’s factory, with no product line of its own to protect or prioritize, had no obvious precedent [5].

That single structural choice — the pure-play foundry model — is the precondition for the fabless design industry that now defines the AI boom. Nvidia, AMD, Apple Silicon, and Broadcom’s custom XPU business all depend on a foundry willing to manufacture a competitor’s chip with the same care as anyone else’s. TSMC does not sell GPUs, and that neutrality is a large part of why customers who compete bitterly against each other in every other respect are all willing to be this one company’s customer at once.

The 2026 numbers

TSMC’s scale is now large enough that its own capital decisions function as a leading indicator for the entire AI hardware cycle. The company revised its 2026 capital expenditure guidance sharply upward, from an original $52-56 billion range to $60-64 billion, with 70-80% of that spend earmarked for advanced-process capacity and 10-20% for advanced packaging [3]. Q2 2026 revenue reached $40.2 billion, up 33.7% year-over-year and 12% quarter-over-quarter — the fifth consecutive record quarter reported at that point in the year [1].

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TSMC 2026 capital expenditure by category (USD billions, midpoint of guidance)
Advanced process (N2/A16) 44.4$B Advanced packaging (CoWoS/SoIC) 11.2$B Other capacity and R&D 6.4$B
Source: Tom's Hardware, citing TSMC guidance, 2026

The Arizona commitment tells the same concentration story from a different angle. TSMC lifted its total US investment pledge to $265 billion, covering at least four additional 2-nanometer fabs beyond what was already under construction [2]. Once every announced facility is complete, roughly 30% of TSMC’s global 2nm-and-beyond capacity is projected to sit in Arizona — the first point at which a complete wafer-to-package supply chain, entirely on US soil, becomes possible for TSMC’s American customers [3].

Why this isn’t really a competitive market

It is tempting to describe TSMC, Intel, and Samsung Foundry as three competitors in one market. At the leading process edge, that framing overstates how contested the field actually is. TSMC’s N2 node is ramping across five fab phases within its first year of production — an unprecedented pace — and N2/A16 capacity is projected to grow at roughly a 70% compound annual rate through 2028 [3]. Reaching that scale requires not just engineering talent but years of accumulated process yield data, a captive customer base large enough to justify the capital outlay before a single wafer ships, and supplier relationships — with ASML for lithography tools chief among them — built up over decades. A new entrant cannot buy its way to parity in a single funding round; it has to out-execute an incumbent that is already compounding.

That is the deeper reason TSMC’s capacity, not any single accelerator’s transistor count, has become the effective ceiling on how much AI hardware the world can produce in a given year. When industry coverage describes advanced-packaging capacity — not wafer starts — as the binding constraint on 2026 AI accelerator output, it is describing a bottleneck inside a single company’s factory floor [1].

A CoWoS advanced-packaging stage with a silicon interposer part-seated under a bonding head, a row of dummy test packages carrying no maker's mark waiting on a stainless tray beside it
Figure 1. Packaging capacity, not the transistor itself, is the binding constraint on 2026 AI-chip output — and TSMC's packaging lines are shared across nearly every major accelerator design in the world.Image prompt and art direction by Brecht Corbeel; image generated to that direction.
Node / capability TSMC position, 2026
Leading-edge logic (2nm-class) Dominant; five fab phases ramping N2 in year one
Advanced packaging (CoWoS, SoIC) Primary supplier for most AI accelerator designs
US domestic capacity ~30% of global 2nm+ capacity, on completion of Arizona buildout
2026 capex $60-64B, ~70-80% to advanced process

What to watch

The honest uncertainty in this story is not whether TSMC stays dominant through 2026 — its backlog and capex guidance both say it will — but what happens as Intel’s 18A and 14A nodes mature, and as Samsung Foundry continues to compete for the same handful of customers large enough to matter. A single company being this central to a trillion-dollar industry’s physical output is not, on its own, evidence of anything sinister; it is the natural consequence of a manufacturing process with such extreme fixed costs that only a few players in the world can afford to stay at the frontier. Whether that concentration eases over the rest of the decade is one of the more consequential open questions in the entire semiconductor industry, and it will be answered by fab construction schedules and yield curves, not by product announcements.