A real, working technical answer to a hard constraint
This cohort’s companion briefing on export-control mechanisms establishes that EUV lithography tools are restricted from reaching Chinese fabs, and that DUV (deep ultraviolet) tools remain available. This briefing covers what Chinese manufacturers actually do with that remaining option: pushing DUV tools through multiple patterning passes — exposing and processing a wafer several times in sequence — to approximate features a single EUV exposure would print directly [1].
How multi-patterning actually works
A single EUV exposure can resolve extremely fine features directly, in one pass, because of its much shorter wavelength. A DUV tool, using longer-wavelength light, cannot resolve those same fine features in one exposure — but by exposing a wafer, processing it, then aligning and exposing it again with a complementary pattern, multiple DUV passes together can approximate a finer final result than any single DUV exposure could achieve alone. This is a genuine, functioning engineering technique, not a myth or an exaggeration — it is a large part of how SMIC’s reported 7nm-class chips actually get made at all [1].
The real, quantifiable cost of the workaround
Multi-patterning is not free. Each additional pass requires a full additional cycle of exposure, development, and alignment — this cohort’s SMIC briefing’s companion piece on foundry economics notes that pitch bought through additional process steps is bought by running the whole loop again, not merely by adjusting one exposure setting. That directly reduces wafer throughput: a chip requiring three DUV passes to achieve a feature size an EUV tool would resolve in one consumes roughly three times the tool-time and introduces three separate opportunities for misalignment or defect introduction, each contributing to the lower yield this cohort’s SMIC briefing documents on Huawei’s Ascend 910C [2].
Why SMIC’s capacity expansion plans make more sense in this light
SMIC’s planned doubling of 7nm capacity in 2026, covered in this cohort’s SMIC strategy briefing, reads differently once the multi-patterning cost is understood explicitly: doubling nominal capacity does not straightforwardly double usable chip output, because a meaningful share of that additional capacity is consumed by the extra passes the DUV workaround requires rather than by net new production [3]. A reader comparing SMIC’s stated capacity figures against a EUV-equipped competitor’s should discount SMIC’s numbers accordingly, rather than treating raw capacity figures as directly comparable across the two different technology bases.
Why this workaround is a genuine engineering achievement, not merely a stopgap
It would be a mistake to read the DUV workaround as evidence of Chinese semiconductor manufacturing being unsophisticated. Multi-patterning at this level of precision is a genuinely difficult engineering achievement in its own right, requiring alignment accuracy across multiple passes that a single-exposure EUV process does not need to solve at all. This cohort’s broader bifurcation briefing describes exactly this kind of adaptation — a structurally different technical approach shaped by a specific constraint, rather than a simple deficient copy of the Western playbook — as evidence of a genuinely parallel semiconductor ecosystem developing its own engineering solutions [4].
The limit this workaround cannot push past indefinitely
Multi-patterning has a practical ceiling: beyond a certain number of additional passes, the cumulative alignment error and yield loss make further patterning both prohibitively expensive and technically unreliable, regardless of how skilled the engineering team executing it is. This is why the technique can approximate near-frontier feature sizes but has not, on the evidence this cohort’s SMIC briefing documents, allowed Chinese fabs to match the newest EUV-equipped nodes directly — there is a real, physics-grounded limit to how far repetition can substitute for a fundamentally higher-resolution exposure tool, distinct from any question of engineering skill or investment.
Why this technique will remain relevant even if controls eventually ease
Even in a scenario where export controls were relaxed, the multi-patterning expertise Chinese fabs have developed would not simply become obsolete — it represents a genuine, transferable manufacturing capability with applications beyond working around a specific restriction, including cost optimization at nodes where EUV access exists but multi-patterning remains cheaper for a given feature size. The technical skill this constraint forced into existence is, in that sense, a durable capability gain independent of how the underlying policy question eventually resolves.
