Why this briefing offers three scenarios, not one forecast
This cohort’s China-focused briefings — SMIC’s yield economics, Huawei’s Ascend roadmap, CXMT’s memory gap, and the DUV lithography workaround — together document a semiconductor ecosystem that is not simply lagging the West on a single, converging timeline, but developing along a genuinely different technical path. Multiple analysts describe this explicitly as a bifurcation: a parallel ecosystem, not a slower copy of the same one [1]. Given genuine uncertainty about where that divergence leads, this briefing constructs three explicit, labeled scenarios rather than picking one as most likely.
Scenario One: Persistent Parallel Divergence
In this scenario, the current trajectory continues largely unchanged: China’s domestic ecosystem keeps advancing on its own multi-patterning DUV and domestic-memory path, achieving steady but incremental improvement, while Western EUV- and High-NA-EUV-equipped fabs continue advancing on their own separate trajectory at a comparable or faster pace [5]. The performance and efficiency gap this cohort’s sources estimate at 5x today, projected toward 17x by 2027 by one cited analysis, would persist directionally, with both ecosystems serving largely separate markets — Chinese domestic AI infrastructure on one technology base, Western and allied infrastructure on another [2].
Scenario Two: A Narrowing Gap
In this scenario, one or more of the specific constraints this cohort documents breaks favorably for China: a genuine yield breakthrough on the existing DUV multi-patterning approach, described in this cohort’s DUV briefing as one of only two developments that would meaningfully change the picture, or a CXMT memory breakthrough closing the gap this cohort’s memory briefing documents [4]. SMIC’s planned 7nm capacity doubling, covered in this cohort’s SMIC strategy briefing, would in this scenario translate into genuinely higher usable output rather than being substantially absorbed by multi-patterning overhead, narrowing the practical gap faster than Scenario One’s steady-state trajectory implies [3].
- Scenario 1 - Persistent divergence
- Scenario 2 - Narrowing gap
- Scenario 3 - Widening gap
Scenario Three: A Widening Gap
In this scenario, Western lithography leadership compounds rather than merely persists: ASML’s High-NA EUV platform, covered in this cohort’s equipment track, reaches broad multi-customer volume production faster than the DUV workaround can be further optimized, and export controls remain in place or tighten further. China’s ecosystem would continue advancing in absolute terms — this cohort’s sources give no indication of stagnation — but the relative gap would widen as the Western frontier’s own rate of advancement outpaces China’s DUV-constrained rate, an outcome consistent with the CFR analysis’s own framing of why it argues current controls should remain in place [2].
What would distinguish which scenario is actually unfolding
Three specific, trackable indicators would distinguish these scenarios empirically rather than rhetorically: SMIC’s actual reported yield trajectory on 7nm-class chips over the next several quarters; whether CXMT’s memory capability closes the reported gap with global HBM producers covered in this cohort’s memory track; and the pace of High-NA EUV’s broader customer adoption, covered in this cohort’s ASML briefing. None of these three indicators has resolved definitively as of this briefing, which is precisely why all three scenarios remain live possibilities rather than one being clearly favored by the evidence collected so far.
Why this matters beyond China specifically
The stakes extend beyond any single country’s semiconductor industry: China alone is projected to generate the highest single-country revenue in the global semiconductor market in 2026, at roughly $224.8 billion [6], meaning any of these three scenarios carries real consequences for the broader $1.3 trillion global market this cohort’s research file documents. Readers should track the specific indicators named above, not general geopolitical sentiment, as the most reliable signal for which of these three futures is actually materializing.
Why a fourth, unlisted scenario deserves acknowledgment
These three scenarios are not exhaustive, and this briefing should not be read as claiming they are. A genuinely disruptive development outside anything this cohort’s current sourcing anticipates — a fundamentally new lithography approach, a policy reversal, or a technology breakthrough on either side not yet visible in available reporting — could produce an outcome none of the three trajectories charted above captures. Scenario analysis of this kind is a tool for structuring uncertainty around known mechanisms, not a claim to have enumerated every possible future; readers should hold these three scenarios as the most useful current framework rather than as a complete accounting of what could happen.
How to revisit this briefing over time
Because this scenario analysis is explicitly time-stamped to mid-2026 sourcing, its value depreciates as new data arrives. A reader returning to this briefing a year from now should treat it as a snapshot of how the uncertainty looked at this specific moment, and should re-examine the three tracked indicators — SMIC yield, CXMT memory capability, and High-NA EUV adoption pace — against whatever more current reporting is available, rather than treating this briefing’s scenarios as a standing, self-updating forecast.
