The opposite job from deposition
This cohort’s companion Applied Materials briefing covers the deposition process — building precise atomic layers up onto a wafer. Lam Research leads the equipment segment that does the opposite: etch, the precision removal of material that turns a deposited, uniformly coated film into an actual patterned circuit structure, typically using a reactive plasma to remove material exactly where a lithography-defined mask leaves it exposed [1].
Why etch has gotten dramatically harder in the HBM era
Ordinary planar etch — removing material from a flat, two-dimensional pattern — is a mature, well-understood process. The etch problem this cohort’s memory-supercycle briefing implicitly depends on is a much harder one: through-silicon vias (TSVs), the deep, narrow vertical channels that let an HBM stack’s individual memory dies connect electrically to each other and to the logic die beneath them [2]. Etching a TSV requires cutting a hole many times deeper than it is wide, with straight walls and a controlled floor, through multiple layers of different materials — a fundamentally harder geometric problem than patterning a flat surface, and one this cohort’s HBM-supercycle briefing identifies TSV throughput as a direct contributor to the current memory shortage.
Etch’s direct connection to the memory shortage this cohort tracks
This cohort’s memory-track briefings establish that the 2026 HBM shortage is a back-end assembly constraint — TSV throughput, hybrid bonding, and TC bonding capacity, not raw wafer supply [3]. Lam Research’s etch equipment sits directly at that bottleneck: TSV etch capacity is one of the specific, physical constraints determining how fast SK hynix, Samsung, and Micron can actually stack additional HBM layers, independent of how much silicon wafer capacity those companies otherwise have available. A reader trying to understand why the memory shortage persists despite strong capital investment across the industry is, in a real sense, asking a question partly answered by Lam Research’s own equipment delivery and qualification timelines.
Etch’s role in advanced packaging more broadly
Beyond HBM specifically, the broader shift toward chiplet-based designs and advanced packaging — covered in this cohort’s TSMC CoWoS and OSAT briefings — depends on precision etch capability at nearly every stage: forming interposer vias, preparing bonding surfaces, and creating the fine structural features that let heterogeneous dies integrate onto a shared substrate. As chip architecture increasingly moves from monolithic dies toward multi-die packages, the etch equipment segment’s importance relative to the historically more headline-grabbing lithography segment has grown correspondingly, part of the broader capital equipment market growth this cohort’s research documents across the whole industry [4].
Why etch rarely gets credit for constraining the industry
Lithography gets blamed for capacity constraints because ASML’s monopoly makes the dependency obvious and easy to explain. Etch capacity constraints are just as real, evidenced directly by this cohort’s own HBM-shortage sourcing, but are distributed across a less concentrated supplier base and a less singular technical narrative, making them easier for casual coverage to overlook entirely. Readers who want an accurate picture of what is actually constraining 2026 AI hardware supply should weight Lam Research’s TSV-etch capacity alongside ASML’s lithography capacity, not treat lithography as the only equipment-layer story worth tracking.
Why etch equipment cannot simply be swapped between applications
A plasma etch tool configured and qualified for one specific process — TSV formation for HBM, say — cannot be trivially repurposed for a different etch application, like patterning a logic transistor’s gate structure, without significant requalification. That specificity means Lam Research’s own capacity allocation decisions, which customer and which process gets priority on a given tool configuration, have real consequences for which segment of the industry feels a capacity crunch first. A surge in HBM-stack demand competing against ordinary logic-chip etch demand for the same underlying equipment expertise, even if not the identical physical tools, is part of the broader capacity-allocation dynamic this cohort’s TSMC CoWoS briefing documents at the packaging layer and this briefing documents at the etch layer beneath it.
The long-term trajectory for etch demand
As chip architecture continues shifting toward taller, more complex 3D structures — deeper HBM stacks, more advanced chiplet interconnects, and the packaging techniques covered throughout this cohort’s equipment track — the etch problems Lam Research has to solve grow more demanding with each generation, not less. That trajectory suggests etch capacity, like packaging capacity, is likely to remain a persistent point of scrutiny in industry capacity planning for years to come, rather than a solved problem that fades from relevance once the current memory shortage eventually eases.
