$$\text{Cost}(\mathcal{P}) \;=\; \alpha \cdot WL(\mathcal{P}) \;+\; \beta \cdot T_{\max}(\mathcal{P}) \;+\; \gamma \cdot \sigma_{\max}(\mathcal{P})$$

Equation 1 · AI Hardware & Semiconductors

Chiplets and Advanced Packaging in Practice: Floorplanning, UCIe, and Thermal Co-Design

This equation states an equality: the expressions on both sides have the same value under the article’s assumptions.

A floorplanning objective built to hold all three properties at once is naturally written as a weighted combination rather than a single term: $\text{Cost}(\mathcal{P}) \;=\; \alpha \cdot WL(\mathcal{P}) \;+\; \beta \cdot T_{\max}(\mathcal{P}) \;+\; \gamma \cdot \sigma_{\max}(\mathcal{P})$. where $\mathcal{P}$ is a candidate placement of dies on the carrier, WL is total interconnect wirelength, $T_{\max}$ is peak steady-state junction temperature anywhere in the assembly, and $\sigma_{\max}$ is peak mechanical stress at any bonded interface. This is a schematic statement of the shape these tools optimize, not a reproduction of any one paper’s exact formula, but it makes the practitioner point concrete: whichever of $\alpha$ , $\beta$ , and $\gamma$ a design team weights most heavily determines where dies actually land, and a…

Meanings in this article

• $\mathcal{P}$: a candidate placement of dies on the carrier, WL is total interconnect wirelength.
• $\alpha$: the whichever of.
• $T_{\max}$: peak steady-state junction temperature anywhere in the assembly.
• $\gamma$: the design team weights most heavily determines where dies actually land.
• $\sigma_{\max}$: peak mechanical stress at any bonded interface.

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