Equation 1 · Part 6 · Chiplets and Advanced Packaging in Practice: Floorplanning, UCIe, and Thermal Co-Design

Symbol T_max

\text{Cost}(\mathcal{P}) \;=\; \alpha \cdot WL(\mathcal{P}) \;+\; \beta \cdot T_{\max}(\mathcal{P}) \;+\; \gamma \cdot \sigma_{\max}(\mathcal{P}),

T_{\max}

What this part means

peak steady-state junction temperature anywhere in the assembly.

Its job in the formula

$T_m$ ax appears in the objective or constraint used by the optimization on the right.

Full expressionSymbol T_maxArticle meaning

Where the article explains it

where $\mathcal{P}$ is a candidate placement of dies on the carrier, WL is total interconnect wirelength, $T_{\max}$ is peak steady-state junction temperature anywhere in the assembly, and $\sigma_{\max}$ is peak mechanical stress at any bonded interface.

The passage around this formula

…properties at once is naturally written as a weighted combination rather than a single term: $\text{Cost}(\mathcal{P}) \;=\; \alpha \cdot WL(\mathcal{P}) \;+\; \beta \cdot T_{\max}(\mathcal{P}) \;+\; \gamma \cdot \sigma_{\max}(\mathcal{P})$ . where $\mathcal{P}$ is a candidate placement of dies on the carrier, WL is total interconnect wirelength, $T_{\max}$ is peak steady-state junction temperature anywhere in the assembly, and $\sigma_{\max}$ is peak mechanical stress at any bonded interface. This is a schematic statement of the shape these tools optimize, not a reproduction of any one paper’s exact formula, but it makes the practitioner point…

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Sources cited in the article section

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