$$C'_{\text{ox}} \;=\; \frac{2\pi\varepsilon_{\text{ox}}}{\ln\!\left(r_{\text{o}}/r_{\text{i}}\right)}$$

Equation 1 · AI Hardware & Semiconductors

How Chiplets and Advanced Packaging Actually Work

This equation states an equality: the expressions on both sides have the same value under the article’s assumptions.

Making the layer flat and fine is a fabrication problem; what that layer then does to a signal is a separate, electrical one, and a through-silicon via is a genuinely awkward electrical object because it is not just a wire — it is a metal core wrapped in a thin insulating liner, sitting inside bulk silicon that is a fairly poor but not negligible conductor in its own right. Treated as a coaxial structure — copper core, oxide liner, conductive silicon beyond it — the liner behaves as a capacitor per unit length, $C'_{\text{ox}} \;=\; \frac{2\pi\varepsilon_{\text{ox}}}{\ln\!\left(r_{\text{o}}/r_{\text{i}}\right)}$. with $r_i$ the via’s metal radius, $r_o$ the outer radius of the oxide liner, and $\varepsilon_{\text{ox}}$ the liner’s permittivity, while the bulk silicon beyond it…

Meanings in this article

• $\varepsilon_{\text{ox}}$: the liner’s permittivity.
• $r_{\text{o}}$: the outer radius of the oxide liner.
• $r_{\text{i}}$: the via’s metal radius.

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