What does this equation mean?

Modern high-rate Ethernet lanes use PAM4 modulation: instead of encoding one bit per symbol as ordinary NRZ signaling does, PAM4 uses four distinct voltage levels to encode two bits per symbol, so a lane’s bit rate runs at twice its baud (symbol) rate rather than matching it one for one. Writing $R_{\mathrm{baud}}$ for the symbol rate and $R_{\mathrm{line}}$ for the resulting line rate, $R_{\mathrm{line}} = 2\,R_{\mathrm{baud}}$. which is exactly the relationship documented for real 400G optics: a 26.5625 Gbaud lane carries 53.125 Gb/s in an eight-lane configuration, and a 53.125 Gbaud lane carries 106.25 Gb/s in a four-lane configuration [ 8 ] . That doubling is not free. Four voltage levels packed into the same signal swing compress the spacing between them, and the same documentation states that PAM4 “considerably reduces the signal-to-noise ratio” relative to NRZ — a roughly 10 dB penalty — which is exactly why a PAM4 transceiver requires a DSP performing equalization and clock recovery, paired with forward error correction, to be usable at all; the guide names RS(544,514) as the industry-standard code, correcting “up to 15 symbol errors within a single codeword” before a frame is considered lost [ 8 ] . The DSP inside a modern transceiver, in other words, is not an incidental feature. It is the component that makes the SNR penalty PAM4 imposes survivable at the rates these fabrics run at.