Equation 6 · Patterning at the Limit: What Actually Happens When a Chip Is Manufactured
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Symbol k_1
a dimensionless process factor absorbing illumination scheme, mask engineering and resist behaviour.
=
The expressions on both sides represent the same quantity under the stated assumptions.
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The lower label selects a particular version, component, or indexed member of the quantity. For example, x₀ and xₜ can be values at different positions.
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What the article says around this equation
where is the exposure wavelength, is the numerical aperture of the projection optics, and is a dimensionless process factor absorbing illumination scheme, mask engineering and resist behaviour. Two-beam interference sets a hard floor: for a periodic line-and-space pattern the smallest printable half-pitch is / (2\,) , which is = 0.25 in the convention where R is a half-pitch. Everything the industry calls resolution enhancement — off-axis illumination, phase shifting, optical proximity correction, inverse lithography — is an attempt to drive down toward that floor without printing garbage.
Sources cited in the article section
- [1] International Roadmap for Devices and Systems 2023 Update: Lithography and Patterning ↗
- [8] TWINSCAN NXT:2050i ↗
These citations give research context. Read each source to check which claims it supports.
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