What does this equation mean?

The reason that fourth side matters can be written down directly. A transistor’s subthreshold swing — how many millivolts of gate voltage it takes to change the drain current by a factor of ten — is well approximated by $S = \frac{kT}{q}\ln(10)\left(1 + \frac{C_{\mathrm{dep}}}{C_{\mathrm{ox}}}\right)$. where $C_{\mathrm{dep}}$ is the capacitance of the depletion region the gate does not fully control and $C_{\mathrm{ox}}$ is the gate’s own oxide capacitance. As $C_{\mathrm{dep}}$ falls toward zero, S falls toward its physical floor of about 60 millivolts per decade at room temperature. Wrapping the gate fully around the channel is, in this equation, a direct attack on $C_{\mathrm{dep}}$ : there is no substrate face left for the depletion region to leak through, because there is no substrate face left at all. A review of nanosheet and nanowire scaling states the qualitative result plainly — gate-all-around structures have better short-channel suppression than the FinFETs they are replacing — while adding a qualification often left out of promotional accounts: the advantage over a fin only shows up once the vertical spacing between stacked sheets is kept below the sheet’s own width, and that spacing is itself bounded below, at around 7 to 8 nanometers, by how thin the gate oxide and metal-gate stack can be made and still work [ 8 ] . The same review notes a real cost on the other side of the ledger: nanosheet and nanowire channels tend to show lower carrier mobility than a conventional planar channel, an effect that worsens at sheet or wire widths below about 10 nanometers because of increased surface-roughness scattering [ 8 ] . Gate-all-around is not a strictly better geometry; it is a geometry that trades mobility for electrostatic control, and the trade only pays off inside a specific dimensional window.