What does this equation mean?

$\eta(t)$ itself is not free to grow indefinitely inside conventional CMOS. Horowitz, Alon, and Patil’s widely cited analysis of chip power scaling made the mechanism explicit: as feature size shrank across recent nodes, supply voltage and threshold voltage stopped scaling down at the historical rate, because pushing them lower drives subthreshold leakage up sharply, and power — not transistor count — became the binding limiter on how fast or how densely a chip could usefully run [ 11 ] . That single fact is the quiet premise behind most edge-AI marketing that promises “10x more efficient” silicon every generation: within one switching technology, each further gain in $\eta(t)$ gets structurally harder to extract, because the voltage floor that sets the energy cost of a single switching event is approached asymptotically rather than crossed. This is analysis built on a documented mechanism, not a forecast by itself — the forecast comes later, once the discontinuity question has been laid out.