AI Datacenter Interconnects in 2035: Scenarios, Signals, and Falsifiable Predictions

Five curves, and what would prove each one wrong

A companion piece in this series argued that the interconnect, not the arithmetic, is the binding constraint on multi-device model work — that once a model no longer fits on one accelerator, reach becomes the design surface. This article takes that argument and points it forward. It asks, for five specific and load-bearing pieces of interconnect technology, what happens between now and 2035, and it commits in advance to the observations that would show each answer wrong.

The five are: how far the per-lane bandwidth curve — electrical and optical — can be extrapolated before a documented constraint intervenes; whether the Ultra Ethernet Consortium’s open transport stack displaces InfiniBand-class fabrics or the two persist split by workload tier; whether co-packaged optics graduates from pilot deployment to default, at the switch and separately at the accelerator package; whether a scale-up domain that spans more than one physical rack — already shipping in one vendor’s roadmap — becomes ordinary rather than exceptional; and what would have to happen for a genuine discontinuity, a change sharp enough that today’s roadmaps stop being useful guides.

Throughout, five kinds of statement are kept visibly separate. A fact is something disclosed in a standard, a specification, or a peer-reviewed paper. A vendor claim is a company’s own statement about its own product, reported as a claim because the company profits from the answer. Analysis works out a consequence of stated facts. A scenario is one internally consistent way the future could go, presented alongside its alternatives rather than as the likely one. A prediction commits to a horizon, states its assumptions plainly, names an observable indicator, and states in advance what would disconfirm it. None of the five trajectories below is a straight-line forecast; each is a documented present extended under a stated assumption, with the assumption itself treated as the interesting and doubtable part.

The documented present

As of this writing, the per-lane electrical signalling rate standardised for high-volume Ethernet is 100 Gb/s per lane, defined by the IEEE P802.3df task force; the successor task force, P802.3dj, is standardising 200 Gb/s PAM-4 per lane alongside longer-reach coherent options, targeting 800 Gb/s and 1.6 Tb/s Ethernet ^{[5, 4]}. On the transport side, the Ultra Ethernet Consortium published its Specification 1.0 on 11 June 2025, an Ethernet-based stack covering transport, congestion control, and physical-layer concerns for AI and HPC workloads at up to millions of endpoints ^[1]. The UALink Consortium published its own 200G 1.0 specification in April 2025, defining a 200 gigatransfers-per-second-per-lane, load/store-capable scale-up interconnect for pods of up to 1,024 accelerators, explicitly positioned as an open alternative to NVIDIA’s proprietary NVLink ^{[2, 3]}.

On optics, NVIDIA has announced co-packaged-optics switch platforms on both sides of the Ethernet/InfiniBand line at once: Quantum-X Photonics for InfiniBand, targeting early-2026 availability, and Spectrum-X Photonics for Ethernet, targeting the second half of 2026, with the company claiming up to 3.5 times lower power per port and a tenfold resiliency improvement from integrating optical engines directly onto switch silicon ^[7] — a vendor claim, not yet an independently measured deployment result. On scale-up reach, NVIDIA’s shipping Vera Rubin NVL72 rack couples 72 GPUs inside one cabinet at 260 TB/s of aggregate NVLink bandwidth ^[8], while the company’s own roadmap disclosure describes a later Rubin Ultra configuration, NVL576, that combines eight separate rack units into a single 576-GPU NVLink domain using “copper and direct optical connections” specifically because copper alone cannot bridge the distance ^[9]. Separately, and already in production rather than on a roadmap, Google’s Ironwood TPU generation uses optical circuit switches to connect 64-chip liquid-cooled cubes into pods and, at the largest configuration, a 9,216-chip, 144-cube superpod, with the optical fabric doubling as the mechanism for routing around a failed cube ^[11] — a multi-rack, optically stitched-together compute domain that already exists, built on optical circuit switching first deployed at hyperscale in Google’s Jupiter fabric ^[10].

On market share, the most recent independent tracking complicates any simple displacement story: Dell’Oro Group reports that in the first quarter of 2026, Ethernet switch sales in AI back-end networks accounted for roughly two-thirds of data-center switch revenue in AI clusters, while InfiniBand sales more than tripled in the same quarter, driven by the ramp of 800 Gb/s switches shipping with NVIDIA’s Blackwell Ultra platform ^[6]. Both fabrics grew sharply at once. That is the documented baseline the five trajectories below extend.

Trajectory one: bandwidth per lane, electrical and optical

Fact. The standardised per-lane electrical rate for Ethernet has moved from 100 Gb/s per lane, defined by P802.3df, to 200 Gb/s PAM-4 per lane under P802.3dj, with 800 Gb/s coherent signalling also standardised for longer single-mode-fibre reaches of 10 to 40 kilometres ^[5]. Set against the wider history — roughly 25 Gb/s per lane around 2010, 50 Gb/s around 2017, 100 Gb/s around 2021 to 2022, and 200 Gb/s targeted for 2026 — the doubling period has been compressing rather than staying fixed: about seven years for the first doubling, about five for the second, about four for the third.

Analysis. A naive extrapolation makes the compressing cadence explicit rather than hiding it. Writing per-lane rate as a function of time, with $R_0$ the most recent standardised rate at time $t_0$ and $T$ the assumed doubling period:

Anchoring at $R_0 = 200$ Gb/s per lane, $t_0 = 2026$, and holding the most recently observed four-year doubling period fixed gives $R(2035) = 200 \cdot 2^{9/4} \approx 950$ Gb/s per lane by 2035 — essentially a 1 Tb/s single electrical lane. That number is offered to be doubted, not believed. The assumption it encodes — that the doubling period keeps compressing on a fixed clock rather than lengthening as channel loss and signal-to-noise margin close in — is exactly the part the standards process itself is already hedging against: P802.3dj did not simply push PAM-4 harder, it added an 800 Gb/s coherent-signalling option specifically for the reaches where intensity-modulated PAM-4 stops being the cheapest way to add bandwidth ^[5]. That is a documented fact about how the last doubling was actually achieved — partly through a different modulation scheme, not only through a faster clock — and it is a reason to expect the next doubling to arrive through some mixture of higher-order modulation, coherent optics, and more parallel lanes rather than through PAM-4 alone continuing to double on schedule.

Prediction. Horizon: end of 2033. The Ethernet standard ratified after P802.3dj will define its headline per-lane rate primarily through a modulation or coherent-signalling change rather than through a straightforward doubling of PAM-4 baud rate on the same channel. Assumption: channel loss and receiver signal-to-noise margin at 224+ gigabaud channels have already been identified by the standards process as harder to close than they were at 112 gigabaud, which is why coherent options entered the roadmap at 800 Gb/s rather than waiting for a still-higher PAM-4 rate. Indicator: the modulation scheme and channel reach specified in the next IEEE 802.3 high-speed Ethernet task force’s adopted baseline. Disconfirmed if the next standard’s headline lane rate is achieved by straightforward PAM-4 baud-rate doubling on the existing channel topology, with no coherent or higher-order-modulation option adopted as a first-class part of the standard.

Trajectory two: Ultra Ethernet and InfiniBand — displacement or coexistence

Fact. Two open, multi-vendor specifications now exist where none did three years ago: the Ultra Ethernet Consortium’s transport stack for scale-out Ethernet fabrics ^[1], and the UALink Consortium’s load/store interconnect for scale-up accelerator pods, explicitly built as an alternative to NVLink ^{[2, 3]}. NVIDIA, the vendor with the largest stake in the outcome, is not betting on one side: it is shipping co-packaged-optics switches for both its InfiniBand line (Quantum-X Photonics) and its Ethernet line (Spectrum-X Photonics) on parallel, months-apart timelines ^[7].

Analysis. The Q1 2026 market data captures the disagreement in one snapshot rather than resolving it: Ethernet held roughly two-thirds of AI back-end switch revenue, and InfiniBand shipments more than tripled in the same quarter on the strength of a single new platform generation ^[6]. Both statements are true at once, and they are consistent with at least two different underlying stories. One story is genuine displacement in progress — Ethernet’s share keeps compounding and InfiniBand’s rebound is a one-generation bump on a fabric headed for a minority role. The other story is coexistence by tier — InfiniBand-class low-latency fabrics keep winning the tightest, most latency-sensitive scale-out tier of a cluster even as Ethernet wins everything larger, more heterogeneous, or more storage- and multi-tenant-adjacent, so both curves can keep growing indefinitely because they are increasingly serving different jobs rather than competing for the same one. The evidence available at this snapshot cannot distinguish these two stories from each other, and this article takes no position on which is correct.

Prediction. Horizon: end of 2029. Independent market trackers will report both fabrics still shipping at meaningful volume — no single fabric type will hold more than 85 percent of AI back-end switch port revenue industry-wide. Assumption: the tiering logic above — InfiniBand-class fabrics retained specifically for the tightest, most synchronisation-sensitive scale-out tier — continues to describe a real, economically defensible segmentation rather than a transitional artefact of incomplete Ethernet-stack maturity. Indicator: the reported vendor and fabric mix in Dell’Oro Group’s or an equivalent tracker’s quarterly AI back-end network reporting. Disconfirmed either way: if one fabric type exceeds 85 percent of port revenue by the horizon (displacement), or if reported revenue for the minority fabric falls in three consecutive quarters with no rebound (a clearer displacement signal than this article currently has grounds to assert).

Trajectory three: co-packaged optics, from pilot deployment to default

Vendor claim. NVIDIA states that moving optical engines directly onto switch silicon cuts power per port by up to 3.5 times relative to pluggable optics and improves resiliency roughly tenfold by reducing the count of separable optical components that can fail, with Quantum-X and Spectrum-X Photonics switches reaching 115 and up to 409.6 terabits per second of switching capacity respectively ^[7]. Those are the vendor’s own figures, from a company selling the product, and they describe engineering targets rather than a field-measured deployment record. A second, chiplet-scale version of the same bet comes from optical-I/O specialists rather than switch vendors: Ayar Labs describes its TeraPHY part as an optical I/O chiplet combining electronic and photonic elements to move chip-to-chip traffic onto light directly at the package edge, positioned as a component other vendors’ accelerator and switch packages could integrate rather than a finished switch product in its own right ^[15] — a narrower, earlier-stage claim than NVIDIA’s, and one this article treats as a signal of ecosystem interest rather than as evidence of near-term volume deployment.

Fact. The peer-reviewed literature independently corroborates the direction of the power claim while flagging different obstacles. A 2024 survey reports that co-packaged designs can bring energy cost down to roughly 5 to 10 picojoules per bit against pluggable modules’ higher baseline, but identifies thermal management, fibre-to-chip coupling loss, and standardisation across vendors as the harder open problems, alongside a documented industry shift away from placing lasers on the photonic die itself, toward external laser sources, because on-die lasers are both the least reliable component and a heat source next to temperature-sensitive optics ^[12].

Analysis. A 2026 preprint pushes further, arguing that the field has been optimising the wrong layer: it contends that photonic-component performance is no longer the binding constraint and that “standardization, serviceability, and thermal-aware co-design” — how a failed optical engine gets diagnosed and replaced inside a densely integrated switch, not how fast the engine itself can modulate — are what actually gate a move from pilot deployment to industry default ^[13]. That is a genuine point of disagreement in the literature: whether the remaining problem is a device problem, which favours continued photonics research, or a systems-integration problem, which favours investment in serviceability and multi-vendor standardisation instead. This article does not adjudicate that disagreement; it notes that the two camps would look for evidence of progress in different places, which is itself a useful thing to watch for.

Prediction. Horizon: end of 2030. Co-packaged optics will be the majority interconnect technology for switch-to-accelerator links at the top-of-fabric tier in at least one major vendor’s shipping product line, but pluggable optics will still be the majority technology at the board edge for general-purpose Ethernet switching outside AI-dedicated fabrics. Assumption: the serviceability and standardisation gap identified by the critical literature narrows enough for large operators to accept it at the highest-value, most bandwidth-constrained tier of the fabric before it narrows enough to displace pluggables everywhere. Indicator: vendor disclosures of the optical interconnect technology used at each tier of shipping AI-fabric products, and any published multi-vendor field-replaceable-optical-engine standard. Disconfirmed if, by the horizon, no major vendor has shipped co-packaged optics in a production AI switch fabric, or if co-packaged optics has already become the majority technology in general-purpose enterprise Ethernet switching as well.

Trajectory four: the scale-up domain crosses the rack boundary

Fact. A scale-up domain larger than one rack is not a hypothetical for 2035; it already exists in production. Google’s Ironwood TPU pods connect 64-chip cubes through optical circuit switches into pods of up to 9,216 chips across 144 cubes, with the same optical fabric used to route around a failed cube by re-establishing circuits among the healthy ones ^[11], building on optical circuit switching Google first deployed at hyperscale in its Jupiter network fabric ^[10]. Separately, NVIDIA’s roadmap disclosure describes a later Rubin Ultra configuration, NVL576, combining eight physically separate rack units — each itself a 72-GPU NVL72-class rack — into one 576-GPU NVLink domain, stating explicitly that copper cannot bridge the inter-rack distance at the target bandwidth and that the link therefore requires “copper and direct optical connections” ^[9].

Analysis. This trajectory is mechanically coupled to the first two. Trajectory one’s rising per-lane rate shortens the reach a passive copper link can cover at acceptable power and error rate; NVIDIA’s own stated reason for needing optical links to complete the NVL576 domain is exactly that reach constraint ^[9]. Trajectory three’s co-packaged optics is one candidate technology for supplying that reach cheaply enough to matter at rack-to-rack distances, not only at switch-to-accelerator distances within one rack. And Google’s already-shipping Ironwood fabric is a working existence proof that an optically stitched multi-rack domain is buildable today, using the different but related tool of circuit switching for reconfigurability and fault routing rather than a fixed load/store NVLink-style domain ^[11].

Prediction. Horizon: end of 2029. A scale-up domain spanning more than one physical rack — whether via a fixed load/store interconnect like NVLink or UALink, or via optical-circuit-switch-mediated pods like Ironwood’s — will be in production use at more than one major accelerator vendor, not only NVIDIA’s. Assumption: the reach constraint driving NVIDIA’s NVL576 design and Google’s OCS-based pod design is a shared physical problem rather than an artefact specific to either company’s package power budget, meaning competing vendors face the same pressure and will reach for a similar solution class. Indicator: publicly disclosed rack counts and interconnect technology for the largest single coherent scale-up or optically reconfigurable pod in each major vendor’s shipping product line. Disconfirmed if, by the horizon, only one vendor has shipped a multi-rack scale-up or OCS-mediated pod domain in production, with competitors’ largest shipping domains still confined to a single rack.

Trajectory five: what could force a discontinuity

Fact. Congestion behaviour in today’s fabrics is not a solved, static property that simply scales — a 2026 characterization study measured congestion across four generations of InfiniBand (EDR, HDR, NDR) plus emerging Ethernet fabrics under both steady and bursty traffic patterns and found scale-dependent behaviour that current congestion-control mechanisms do not uniformly handle well ^[14]. That is evidence that the interconnect’s problems do not stay fixed as systems grow; new failure and contention modes appear at new scales, which is itself a slow-moving pressure toward architectural change even without a single dramatic breakthrough.

Scenario. The sharper, lower-probability candidate for a genuine discontinuity is optical switching moving from a specialised reconfiguration role into a general default for scale-out fabrics, not only scale-up ones. Google’s optical circuit switches today serve a specific function — dynamic topology reconfiguration and fault routing within and between Ironwood pods ^[11], building on the same approach’s earlier hyperscale deployment in Jupiter ^[10] — rather than replacing electronic packet switching generally. A discontinuity scenario is one in which the serviceability and integration gap that the critical co-packaged-optics literature identifies ^[13] closes fast enough, and optical-switch cost and radix improve fast enough, that a reconfigurable optical layer stops being a scale-up or pod-scale specialty and becomes the default way large fabrics are built at every tier — a change that would make several of this article’s other trajectories, framed as continuations of an electrical-and-pluggable-optics present, obsolete as descriptions of the mainstream rather than merely wrong about a date.

Prediction. Horizon: end of 2032. No vendor will have shipped a production AI fabric in which optical circuit switching or an equivalent reconfigurable photonic layer has replaced electronic packet switching as the default at the scale-out tier connecting pods to each other, across an entire datacenter-scale cluster. This is stated as the conservative, base-rate expectation precisely so the discontinuity scenario has a clean test. Assumption: the systems-integration and serviceability barriers identified in trajectory three apply with at least as much force to switch-scale optical reconfiguration as to co-packaged optics at the board edge, since both require field-serviceable, multi-vendor-interoperable optical hardware at a scale current supply chains have not yet demonstrated. Indicator: vendor and hyperscaler disclosures of the switching technology used at the scale-out, cross-pod tier of newly built AI-dedicated fabrics. Disconfirmed if, before the horizon, a major operator discloses a production cluster where reconfigurable optical switching, rather than electronic packet switching, is the default technology connecting pods to each other across the full fabric.

Two axes, four scenarios toward 2035

Crossing trajectory two’s displacement-or-coexistence question with trajectories one, three, four, and five’s smooth-scaling-or-discontinuity question gives four scenarios. None is presented as the likely one.

Scenario A: Smooth Convergence. Ethernet, carried by the Ultra Ethernet stack, absorbs the scale-out tier fully and InfiniBand-class fabrics recede to a shrinking niche, while per-lane rates, co-packaged optics adoption, and multi-rack scale-up domains all continue on the smooth curves described above, without a forced architectural break. Horizon: InfiniBand’s AI back-end port-revenue share below 15 percent by 2031; the physical curves in trajectories one, three, and four continuing without a discontinuity event through 2035. Assumptions: the tiering logic in trajectory two turns out not to describe a durable segmentation — Ethernet’s stack closes whatever latency or determinism gap currently justifies InfiniBand’s tightest-tier role. Observable indicators: InfiniBand’s quarterly port-revenue share trending down for multiple consecutive quarters without a rebound comparable to the one recorded in Q1 2026; continued incremental (not discontinuous) per-lane rate, co-packaged-optics adoption, and scale-up-domain growth. Disconfirmation: falsified if InfiniBand-class fabrics retain more than 20 percent AI back-end port revenue through 2031, or if any of trajectories one, three, or four shows a sharp discontinuity instead of smooth continuation.

Scenario B: Smooth Coexistence. Ethernet and InfiniBand-class fabrics persist split by tier indefinitely — Ethernet for the larger, more heterogeneous scale-out fleet, InfiniBand-class or NVLink/UALink-class fabrics for the tightest scale-up tier — while the physical curves continue smoothly on both sides of that split. Horizon: both fabric types still shipping at more than 15 percent AI back-end port revenue through 2032; smooth continuation of the other four trajectories through 2035. Assumptions: the tiering logic is a durable, economically rational segmentation rather than a transitional state; no single physical constraint forces one tier’s technology to be abandoned. Observable indicators: stable or gently shifting, rather than collapsing, relative port-revenue shares across multiple years; both fabric families continuing to receive new generational product releases from multiple vendors. Disconfirmation: falsified if either fabric type’s share falls below 15 percent and continues falling for three or more consecutive years, or if a discontinuity event (scenario C or D) occurs in any of trajectories one, three, four, or five.

Scenario C: Forced Convergence. A discontinuity — most plausibly the optical-switching generalisation described in trajectory five — arrives and specifically accelerates convergence onto a single dominant fabric type faster than smooth-curve extrapolation would predict, because the new technology erases the latency or determinism advantage that previously justified keeping a separate scale-up tier. Horizon: a disclosed, production-scale reconfigurable-optical or equivalent discontinuity event by 2030-2031; visibly accelerated fabric-type consolidation within two to three years of that event. Assumptions: the discontinuity, when it arrives, happens to remove specifically the technical justification for fabric-type segmentation rather than some other constraint. Observable indicators: a sudden, coordinated shift in multiple vendors’ fabric-technology disclosures within the same one-to-two-year window, following a specific named technology event. Disconfirmation: falsified if a discontinuity event occurs (per trajectory five’s indicator) without a corresponding acceleration in fabric-type consolidation, or if consolidation happens without any discontinuity event preceding it (which would indicate scenario A instead).

Scenario D: Forced Divergence. A discontinuity occurs, but rather than erasing the distinction between fabric tiers, it deepens it — for example, a co-packaged-optics or optical-switching breakthrough disproportionately benefits the tightest, most latency-sensitive scale-up tier, letting it pull further ahead of commodity Ethernet scale-out rather than converging with it. Horizon: a disclosed discontinuity event by 2030-2031; a widening, rather than narrowing, performance or bandwidth gap between scale-up and scale-out tiers visible by 2035. Assumptions: the discontinuity’s benefits are not uniformly distributable across fabric types because of cost, licensing, or physical placement constraints specific to the tightest tier. Observable indicators: a discontinuity event (per trajectory five) followed by a growing rather than shrinking disclosed bandwidth or latency gap between top-of-rack scale-up links and cross-pod scale-out links in vendor product lines. Disconfirmation: falsified if a discontinuity event occurs and the tier gap narrows rather than widens, or if no discontinuity event occurs at all through the horizon.

What survives across all four cells, and the wildcard none of them names

One fact holds regardless of which cell the industry lands in: the reach-versus-rate coupling connecting trajectories one and four is not contingent on any of the four scenarios above. As per-lane rates rise, copper’s viable reach at acceptable power shrinks, and that pressure exists whether Ethernet and InfiniBand-class fabrics converge or coexist, and whether or not a discontinuity occurs. It is why NVIDIA’s own stated reason for the NVL576 domain needing optical rather than purely copper links is a physical one, not a competitive one ^[9], and it is why every major vendor is investing in some form of optical reach extension regardless of which side of the Ethernet-versus-InfiniBand question it is betting on.

The wildcard none of the four scenarios names is a fabric technology that does not appear in any 2026 roadmap at all — not a faster version of UEC, UALink, NVLink, or InfiniBand, but something built photonic-native from the start, with no electrical fallback path, of a kind no consortium has yet specified. Nothing in the sources behind this article points to such a technology existing today even at prototype stage; it is named here only because a genuine discontinuity, by definition, is not visible in advance from inside the roadmaps that would be disrupted by it.

What to take away

Five things are true about AI datacenter interconnects at the point this article was written, and none of them is a prediction: per-lane rates are standardised through 200 Gb/s with a compressing but not obviously indefinite doubling cadence; two open specifications now exist to challenge NVIDIA’s proprietary interconnects at both the scale-out and scale-up tiers; co-packaged optics is shipping on vendor roadmaps with vendor-stated power and resiliency gains that the independent literature partially corroborates and partially contests on different grounds; a scale-up domain spanning more than one physical rack already exists in production at one vendor and is roadmapped at another; and current fabrics already show scale-dependent congestion behaviour that no single technology change has yet resolved. Everything beyond those five documented facts in this article is either a vendor’s own claim about its own product, an analysis of what a stated assumption implies, or a scenario and prediction carrying an explicit horizon and an explicit way to be proven wrong. The discipline that matters most for a reader returning to this piece in 2035 is not which scenario turned out closest to right — it is checking each prediction’s stated indicator against what actually happened, and noticing which assumptions held and which quietly stopped being true along the way.