Equation 26 · What an AI Accelerator Actually Is: Silicon, Packaging, and the Memory It Can Reach
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the latency term grows linearly in. Read the equation part by part below; each part has a contextual explanation and a link to its mathematical background.
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Their cost has a shape worth internalising. For the standard ring formulation of an all-reduce over p devices and N bytes, the operation decomposes into a reduce-scatter followed by an all-gather, each of p - 1 steps in which every device sends N/p bytes. Total time is approximately
Sources cited in the article section
- [11] NVIDIA Collective Communication Library (NCCL) Documentation ↗
- [9] NVIDIA Hopper Architecture In-Depth ↗
- [3] TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings ↗
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