Equation 8 · Patterning at the Limit: What Actually Happens When a Chip Is Manufactured
What does this equation mean?
Read the formula alongside the article passage below. Each part has a deeper page with its role in the equation, the supporting passage and nearby citations.
a dimensionless process factor absorbing illumination scheme, mask engineering and resist behaviour. Read the equation part by part below; each part has a contextual explanation and a link to its mathematical background.
Read it piece by piece
Symbol k_1
a dimensionless process factor absorbing illumination scheme, mask engineering and resist behaviour.
subscript
The lower label selects a particular version, component, or indexed member of the quantity. For example, x₀ and xₜ can be values at different positions.
How to interpret it
Read this expression with the definitions, units, and assumptions supplied by the article.
What the article says around this equation
where is the exposure wavelength, is the numerical aperture of the projection optics, and is a dimensionless process factor absorbing illumination scheme, mask engineering and resist behaviour. Two-beam interference sets a hard floor: for a periodic line-and-space pattern the smallest printable half-pitch is / (2\,) , which is = 0.25 in the convention where R is a half-pitch. Everything the industry calls resolution enhancement — off-axis illumination, phase shifting, optical proximity correction, inverse lithography — is an attempt to drive down toward that floor without printing garbage.
Sources cited in the article section
- [1] International Roadmap for Devices and Systems 2023 Update: Lithography and Patterning ↗
- [8] TWINSCAN NXT:2050i ↗
These citations give research context. Read each source to check which claims it supports.
Return to Patterning at the Limit: What Actually Happens When a Chip Is Manufactured