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Equation 14 · Part 8 · Patterning at the Limit: What Actually Happens When a Chip Is Manufactured

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EPE=σoverlay2+σCD2+σLER2,\mathrm{EPE} = \sqrt{\sigma_{\mathrm{overlay}}^{2} + \sigma_{\mathrm{CD}}^{2} + \sigma_{\mathrm{LER}}^{2}},
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What this part means

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The passage around this formula

If the contributing terms were independent and Gaussian, the budget would combine as EPE=σoverlay2+σCD2+σLER2\mathrm{EPE} = \sqrt{\sigma_{\mathrm{overlay}}^{2} + \sigma_{\mathrm{CD}}^{2} + \sigma_{\mathrm{LER}}^{2}}. and the largest term would dominate. That independence assumption is exactly what makes the model useful and exactly where it is weakest: overlay and local variability share common causes through the same exposure, the same etch and the same stack. Treat the expression as a budgeting device, not a physical law. The roadmap cites published numerical simulations estimating that overlay takes about 40 per cent of the edge placement error budget and line-edge roughness about 25 per cent [ 1 ] . On that split, placement — not printing — is the single largest contributor.

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Sources cited in the surrounding passage

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