Symbol B

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The roofline model, introduced by Williams, Waterman, and Patterson in 2009, gives the concept its formal shape. It plots two independent ceilings on the same chart: the chip’s peak arithmetic throughput (operations per second) on one axis, and its peak memory bandwidth (bytes per second) combined with a workload-specific ratio on the other. That ratio — arithmetic intensity — is defined as the number of floating-point operations performed per byte of data moved between memory and the arithmetic units [ 4 ] . A workload’s achievable throughput is bounded by whichever ceiling it hits first: $I = \frac{\text{FLOPs performed}}{\text{bytes moved}}, \qquad P_{\text{achievable}} = \min\left(P_{\text{peak compute}},\; I \times BW_{\text{peak memory}}\right)$. When a workload’s intensity I is high enough that I $\times$ B$W_{\text{peak memory}}$…

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