subscript

The passage around this formula

Here $T_{\mathrm{peak}}$ is the arithmetic identity fixed at design time, $U_{\mathrm{hw}}$ $\in$ (0,1] is the fraction of cycles the hardware keeps its arithmetic units genuinely busy on whatever workload is thrown at it, and $U_{\mathrm{compiler}}$ $\in$ (0,1] is the fraction of a program’s theoretically available parallelism that the compiler or mapper actually manages to expose to the hardware. A GPU’s SIMT scheduler mostly targets $U_{\mathrm{hw}}$ , hiding latency and filling gaps dynamically regardless of how well the source program was written. A systolic array and a statically scheduled dataflow chip push almost the entire burden onto $U_{\mathrm{compiler}}$ : there is no runtime mechanism left…

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