Equation 3 · A Rising FLOPs-per-Byte Ratio Explains Why Nvidia Split the Chip in Two
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The reason arithmetic intensity is the right lens, rather than either raw FLOPs or raw bandwidth alone, is that a chip’s advertised compute figure is only ever a ceiling a given workload may or may not reach. Below a workload-specific threshold — the roofline model’s “ridge point,” the arithmetic intensity at which a chip stops being memory-bound and starts being compute-bound — throughput is capped by bytes moved, not by tensor-core count, and every FLOP of purchased silicon sitting past that ceiling is, for that workload, silicon paid for and not used. A rising does not by itself say anything about whether real workloads are keeping pace with it. It says that the ceiling keeps…
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The reason arithmetic intensity is the right lens, rather than either raw FLOPs or raw bandwidth alone, is that a chip’s advertised compute figure is only ever a ceiling a given workload may or may not reach. Below a workload-specific threshold — the roofline model’s “ridge point,” the arithmetic intensity at which a chip stops being memory-bound and starts being compute-bound — throughput is capped by bytes moved, not by tensor-core count, and every FLOP of purchased silicon sitting past that ceiling is, for that workload, silicon paid for and not used. A rising does not by itself say anything about whether real workloads are keeping pace with it. It says that the ceiling keeps climbing, and that whatever a chip’s design target is, its designers are betting on workloads with steadily higher arithmetic intensity to justify building it. Six generations of Nvidia data-center GPUs is a fairly direct record of what Nvidia has been betting on.
Sources cited in the article section
- [4] NVIDIA H100 Tensor Core GPU Datasheet ↗
- [5] Hopper (microarchitecture) ↗
- [6] NVIDIA HGX Platform (B200 specifications) ↗
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