#Tensor Core

Two visibly different data-center accelerator boards side by side on open test fixtures, one ringed by a tight cluster of stacked memory packages close to its die, the other surrounded by a wider grid of individually socketed memory chips

A Rising FLOPs-per-Byte Ratio Explains Why Nvidia Split the Chip in Two

FLOPs per byte, tracked across six Nvidia data-center GPU generations from the 2016 Tesla P100 to 2026's Rubin, climbs from under 30 to over 1,500 — and then the ratio forks into two numbers the day Nvidia ships a GPU with no HBM in it at all.

By Brecht Corbeel · September 9, 2026 · 18 min read

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