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Equation 1 · Part 4 · AI Accelerator Architecture in 2035: Scenarios, Signals, and Falsifiable Predictions

Symbol F_0

F(t)B(t)=F0B0(rFrB)t/2\frac{F(t)}{B(t)} = \frac{F_0}{B_0}\left(\frac{r_F}{r_B}\right)^{t/2}
F0F_0

What this part means

F0F_0 occurs above the fraction bar. The numerator is divided by the entire denominator below it.

Its job in the formula

F0F_0 occurs above the fraction bar. The numerator is divided by the entire denominator below it.

The passage around this formula

The structural fact behind every accelerator roadmap for a decade has been that peak arithmetic throughput has scaled roughly three times every two years while DRAM bandwidth has scaled roughly 1.6 times and interconnect bandwidth roughly 1.4 times over the same interval [ 1 ] . Analysis. Extending those three exponents unchanged from a 2024 baseline to 2035 — eleven years, or 5.5 doubling periods at the two-year cadence the source measures — gives a compact way to see how much the imbalance would compound if nothing structural intervenes: F(t)B(t)=F0B0(rFrB)t/2\frac{F(t)}{B(t)} = \frac{F_0}{B_0}\left(\frac{r_F}{r_B}\right)^{t/2}. With rFr_F ≈\approx 3.0 and rBr_B ≈\approx 1.6 for DRAM bandwidth, (rFr_F/rBr_B)^{5.5} = (1.875)^{5.5} ≈\approx 32 : the ratio of peak…

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Sources cited in the surrounding passage

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